The present invention relates to silicon power semiconductor devices and, more particularly, to a silicon semiconductor die having an efficient and reliable edge termination zone.
PN junctions within semiconductor devices are not infinite, terminating at the edge zones of a die. This edge effect limits the device breakdown voltage below the ideal value, Vbrpp, that is set by the infinite parallel plane junction. Care must be taken to ensure proper and efficient termination of the junction at the edge of the die; if the junction is poorly terminated, the device breakdown voltage can be as low as 10-20% of the ideal case. Such severe degradation in breakdown voltage can seriously compromise device design and lead to reduced current rating as well. In addition, an inefficient edge termination makes a device unstable and unreliable if the device is operated in a harsh environment or over a long period of time.
Various edge termination techniques have been developed, including, for example, field plate (FP), described in F. Conti and M. Conti, xe2x80x9cSurface breakdown in silicon planar diodes equipped with field plate,xe2x80x9d Solid State Electronics, Vol. 15, pp 93-105, the disclosure of which is incorporated herein by reference. Another edge termination approach is field limiting rings (FLR), described in Kao and Wolley, xe2x80x9cHigh voltage planar p-n junctions,xe2x80x9d Proc. IEEE, 1965, Vol. 55, pp 1409-1414, the disclosure of which is incorporated herein by reference. Further edge termination structures utilized variable lateral doping concentration (VLD), described in R. Stengl et al., xe2x80x9cVariation of lateral doping as a field terminator for high-voltage power devicesxe2x80x9d, IEEE Trans. Electron Devices, 1986, Vol. ED-33, No. 3, pp 426-428, and junction termination extension (JTE), described in V. A. K. Temple, xe2x80x9cJunction termination extension, a new technique for increasing avalanche breakdown voltage and controlling surface electric field in p-n junction,xe2x80x9d IEEE International Electron Devices Meeting Digest, 1977 Abstract 20.4, pp 423-426, the disclosures of which are incorporated herein by reference.
The purpose of all these various techniques is to reduce electron-hole avalanche generation by lowering the peak electric field strength along the semiconductor surface and thereby shifting the avalanche breakdown location into the bulk of the device. To achieve this goal, the width of the edge termination zone (Ledge) has to be several times higher than the depletion width (Wpp) of the parallel-plane portion of the PN junction. For example, if Ledge=2.98Wpp, 98.7% of Vbrpp can be achieved when an xe2x80x9cideal edge termination,xe2x80x9d as described in Drabe and Sittig, xe2x80x9cTheoretical investigation of plane junction termination,xe2x80x9d Solid State Electronics, 1996, Vol. 3, No. 3, pp 323-328, the disclosure of which is incorporated herein by reference, is used. In practice, a longer Ledge than the theoretical value should be used to guarantee device reliability. However, it is very important to point out that, even with very efficient edge termination, electron-hole impact generation at a rate of about 1xc3x971018 pairs/cm3.s, still exists along the semiconductor surface.
A silicon semiconductor die of the present invention comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone.
Further in accordance with the present invention is a process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer. A well region of a second, opposite conduction type is formed at the upper surface of the upper layer adjacent the edge termination zone, and an oxide layer is formed over the upper layer and edge termination zone.